| Approximate Karatsuba multiplier for error-resilient applications R Jain, N Pandey AEU-International Journal of Electronics and Communications 130, 153579, 2021 | 13 | 2021 |
| Hybrid Dynamic CML with Modified Current Source (H-MDyCML): A Low-Power Dynamic MCML Style R Jain, K Gupta, N Pandey Advances in Electrical and Electronic Engineering 19 (1), 57-65, 2021 | 3 | 2021 |
| Realization of regula-falsi iteration based double precision floating point division R Jain, N Pandey 2020 4th International Conference on Trends in Electronics and Informatics …, 2020 | 2 | 2020 |
| FPGA Implementation of DHT Through Parallel and Pipeline Structure R Jain, P Jain 2021 International Conference on Computer Communication and Informatics …, 2021 | 1 | 2021 |
| FPGA implementation of recursive algorithm of DCT R Jain, P Jain Proceedings of International Conference on Artificial Intelligence and …, 2020 | 1 | 2020 |
| Booth-Encoded Karatsuba: A Novel Hardware-Efficient Multiplier R Jain, K Pahwa, N Pandey Advances in Electrical and Electronic Engineering 19 (3), 272-281, 2021 | | 2021 |
| Realization of Systolic Architecture of Discrete Cosine Transform R Jain, P Jain 2021 International Conference on Computer Communication and Informatics …, 2021 | | 2021 |
| Realization of Various Topologies of Adders Based on H-Dycml R Jain, N Pandey | | |
