| Identification and rejuvenation of nbti-critical logic paths in nanoscale circuits M Jenihhin, G Squillero, TS Copetti, V Tihhomirov, S Kostin, M Gaudesi, ... Journal of Electronic Testing 32, 273-289, 2016 | 21 | 2016 |
| Multiple stuck-at-fault detection theorem R Ubar, S Kostin, J Raik 2012 IEEE 15th International Symposium on Design and Diagnostics of …, 2012 | 21 | 2012 |
| Hierarchical identification of NBTI-critical gates in nanoscale logic S Kostin, J Raik, R Ubar, M Jenihhin, F Vargas, LMB Poehls, TS Copetti 2014 15th Latin American Test Workshop-LATW, 1-6, 2014 | 15 | 2014 |
| Spice-inspired fast gate-level computation of nbti-induced delays in nanoscale logic S Kostin, J Raik, R Ubar, M Jenihhin, T Copetti, F Vargas, LB Poehls 2015 IEEE 18th International Symposium on Design and Diagnostics of …, 2015 | 14* | 2015 |
| Accurate dialysis dose evaluation and extrapolation algorithms during online optical dialysis monitoring I Fridolin, D Karai, S Kostin, R Ubar IEEE Transactions on Biomedical Engineering 60 (5), 1371-1377, 2012 | 14 | 2012 |
| Embedded fault diagnosis in digital systems with BIST R Ubar, S Kostin, J Raik Microprocessors and Microsystems 32 (5-6), 279-287, 2008 | 9 | 2008 |
| Multiple fault diagnosis with BDD based boolean differential equations R Ubar, J Raik, S Kostin, J Kõusaar 2012 13th Biennial Baltic Electronics Conference, 77-80, 2012 | 8 | 2012 |
| About robustness of test patterns regarding multiple faults R Ubar, S Kostin, J Raik 2012 13th Latin American Test Workshop (LATW), 1-6, 2012 | 8 | 2012 |
| Block-level fault model-free debug and diagnosis in digital systems R Ubar, S Kostin, J Raik 2009 12th Euromicro Conference on Digital System Design, Architectures …, 2009 | 8 | 2009 |
| Identifying nbti-critical paths in nanoscale logic R Ubar, F Vargas, M Jenihhin, J Raik, S Kostin, LB Poehls 2013 Euromicro Conference on Digital System Design, 136-141, 2013 | 6 | 2013 |
| Embedded diagnosis in digital systems R Ubar, S Kostin, J Raik 2008 26th International Conference on Microelectronics, 421-424, 2008 | 6 | 2008 |
| Fast identification of true critical paths in sequential circuits R Ubar, S Kostin, M Jenihhin, J Raik, L Jürimägi Microelectronics Reliability 81, 252-261, 2018 | 5 | 2018 |
| Gate-level modelling of NBTI-induced delays under process variations T Copetti, G Medeiros, LB Poehls, F Vargas, S Kostin, M Jenihhin, J Raik, ... 2016 17th Latin-American Test Symposium (LATS), 75-80, 2016 | 5 | 2016 |
| Rejuvenation of nanoscale logic at NBTI-critical paths using evolutionary TPG N Palermo, V Tihhomirov, TS Copetti, M Jenihhin, J Raik, S Kostin, ... 2015 16th Latin-American Test Symposium (LATS), 1-6, 2015 | 5 | 2015 |
| How to Prove that a Circuit is Fault-Free? R Ubar, S Kostin, J Raik 2012 15th Euromicro Conference on Digital System Design, 427-430, 2012 | 5 | 2012 |
| Fault diagnosis in integrated circuits with BIST R Ubar, S Kostin, J Raik, T Evartson, H Lensen 10th Euromicro Conference on Digital System Design Architectures, Methods …, 2007 | 5 | 2007 |
| Hierarchical Timing-Critical Paths Analysis in Sequential Circuits L Jürimagi, R Ubar, M Jenihhin, J Raik, S Devadze, S Kostin 2018 28th International Symposium on Power and Timing Modeling, Optimization …, 2018 | 2 | 2018 |
| Exact parallel critical path fault tracing to speed-up fault simulation in sequential circuits J Kõusaar, S Kostin, R Ubar, S Devadze, J Raik International Journal of Microelectronics and Computer Science 9 (1), 9--18, 2018 | 2 | 2018 |
| A scalable technique to identify true critical paths in sequential circuits R Ubar, S Kostin, M Jenihhin, J Raik 2017 IEEE 20th International Symposium on Design and Diagnostics of …, 2017 | 2 | 2017 |
| VLSI-SoC: System-on-Chip in the Nanoscale Era–Design, Verification and Reliability T Hollstein, J Raik, S Kostin, A Tšertov, I O'Connor, R Reis Springer International Publishing, 2017 | 2 | 2017 |
