| A 1.2 V 20 nm 307 GB/s HBM DRAM with at-speed wafer-level IO test scheme and adaptive refresh considering temperature distribution K Sohn, WJ Yun, R Oh, CS Oh, SY Seo, MS Park, DH Shin, WC Jung, ... IEEE Journal of Solid-State Circuits 52 (1), 250-260, 2016 | 95 | 2016 |
| A 1.2 V 20 nm 307 GB/s HBM DRAM with at-speed wafer-level IO test scheme and adaptive refresh considering temperature distribution K Sohn, WJ Yun, R Oh, CS Oh, SY Seo, MS Park, DH Shin, WC Jung, ... 2016 IEEE International Solid-State Circuits Conference (ISSCC), 316-317, 2016 | 95 | 2016 |
| A 0.1-to-1.5 GHz 4.2 mW all-digital DLL with dual duty-cycle correction circuit and update gear circuit for DRAM in 66nm CMOS technology WJ Yun, HW Lee, D Shin, SD Kang, JY Yang, HO Lee, DU Lee, S Sim, ... 2008 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2008 | 41 | 2008 |
| Semiconductor device having a plurality of repair fuse units J Lee, H Lee, S Shin, H Choi US Patent 8,110,892, 2012 | 17 | 2012 |
| Semiconductor device having a plurality of repair fuse units JW Lee, HD Lee, SH Shin, HH Choi US Patent 8,698,276, 2014 | 14 | 2014 |
| Multi-slew-rate output driver and optimized impedance-calibration circuit for 66nm 3.0 Gb/s/pin DRAM interface DU Lee, SD Kang, NK Park, HW Lee, YK Choi, JW Lee, SW Kwack, ... 2008 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2008 | 14 | 2008 |
| Memory device having a shareable error correction code cell array HJ Kim, KIM Soo-Hyeong, S Shin, J Ju-Yun, H Song, KM Sohn, ... US Patent 9,859,022, 2018 | 12 | 2018 |
| Stack bank type semiconductor memory apparatus capable of improving alignment margin K Seung-Wook, S Shin, KS Song US Patent 9,123,395, 2015 | 12 | 2015 |
| System package DU Lee, SH Shin US Patent App. 13/720,533, 2014 | 12 | 2014 |
| Device and system including adaptive repair circuit S Shin, LEE Hae-Suk, J Han-Vit, KM Sohn US Patent 9,727,409, 2017 | 10 | 2017 |
| Repair circuit and repair method of semiconductor apparatus XH Cui, JW Lee, SH Shin US Patent 8,514,641, 2013 | 10 | 2013 |
| Test circuit and method of semiconductor integrated circuit SH Shin, TY Lee US Patent App. 13/421,087, 2012 | 8 | 2012 |
| Semiconductor device and method for driving the same S Shin, HD Lee, JW Lee, HH Choi US Patent 8,171,358, 2012 | 8 | 2012 |
| Semiconductor circuit apparatus SH Shin US Patent App. 12/833,066, 2011 | 8 | 2011 |
| A 1.6 V 3.3 Gb/s GDDR3 DRAM with dual-mode phase-and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS HW Lee, WJ Yun, YK Choi, HH Choi, JJ Lee, KH Kim, SD Kang, JY Yang, ... 2009 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2009 | 8 | 2009 |
| Semiconductor apparatus SH Shin, KS Lee US Patent 8,687,443, 2014 | 7 | 2014 |
| Semiconductor device S Shin, H Lee, J Choi US Patent 7,973,590, 2011 | 6 | 2011 |
| Design of non-contact 2Gb/s I/O test methods for high bandwidth memory (HBM) H Lee, S Kang, HS Yu, WJ Yun, JH Jung, S Ahn, WS Kim, B Kil, YC Sung, ... 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC), 169-172, 2016 | 5 | 2016 |
| Integrated circuit DU Lee, S Shin US Patent App. 13/716,296, 2013 | 5 | 2013 |
| Semiconductor memory apparatus and test method thereof TS Yun, HD Lee, JG Choi, SJ Byeon, SH Shin US Patent 8,300,496, 2012 | 5 | 2012 |
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