| On-chip learning for domain wall synapse based fully connected neural network D Bhowmik, U Saxena, A Dankar, A Verma, D Kaushik, S Chatterjee, ... Journal of Magnetism and Magnetic Materials 489, 165434, 2019 | 53 | 2019 |
| Low-energy implementation of feed-forward neural network with back-propagation algorithm using a spin-orbit torque driven skyrmionic device U Saxena, D Kaushik, M Bansal, U Sahu, D Bhowmik IEEE Transactions on Magnetics 54 (11), 1-5, 2018 | 21 | 2018 |
| A 35.5-127.2 tops/w dynamic sparsity-aware reconfigurable-precision compute-in-memory sram macro for machine learning M Ali, I Chakraborty, U Saxena, A Agrawal, A Ankit, K Roy IEEE Solid-State Circuits Letters 4, 129-132, 2021 | 20 | 2021 |
| Towards adc-less compute-in-memory accelerators for energy efficient deep learning U Saxena, I Chakraborty, K Roy 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 624-627, 2022 | 13 | 2022 |
| On-chip learning in a conventional silicon MOSFET based analog hardware neural network N Dey, J Sharda, U Saxena, D Kaushik, U Singh, D Bhowmik 2019 IEEE Biomedical Circuits and Systems Conference (BioCAS), 1-4, 2019 | 12 | 2019 |
| Revisiting stochastic computing in the era of nanoscale nonvolatile technologies A Agrawal, I Chakraborty, D Roy, U Saxena, S Sharmin, M Koo, Y Shim, ... IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28 (12 …, 2020 | 11 | 2020 |
| Compute-in-memory technologies and architectures for deep learning workloads M Ali, S Roy, U Saxena, T Sharma, A Raghunathan, K Roy IEEE Transactions on Very Large Scale Integration (VLSI) Systems 30 (11 …, 2022 | 8 | 2022 |
| Embracing stochasticity to enable neuromorphic computing at the edge A Agrawal, D Roy, U Saxena, K Roy IEEE Design & Test 38 (6), 28-35, 2021 | 5 | 2021 |
| Hardware/software co-design with adc-less in-memory computing hardware for spiking neural networks MPE Apolinario, AK Kosta, U Saxena, K Roy IEEE Transactions on Emerging Topics in Computing, 2023 | 4 | 2023 |
| Skyrmionic implementation of spike time dependent plasticity (STDP) enabled spiking neural network (SNN) under supervised learning scheme U Sahu, K Goyal, U Saxena, T Chavan, U Ganguly, D Bhowmik 2018 4th IEEE International Conference on Emerging Electronics (ICEE), 1-6, 2018 | 3 | 2018 |
| Ferroelectric capacitors and field-effect transistors as in-memory computing elements for machine learning workloads E Yu, GK K, U Saxena, K Roy Scientific Reports 14 (1), 9426, 2024 | | 2024 |
| HCiM: ADC-Less Hybrid Analog-Digital Compute in Memory Accelerator for Deep Learning Workloads S Negi, U Saxena, D Sharma, K Roy arXiv preprint arXiv:2403.13577, 2024 | | 2024 |
| Sparsity-aware reconfigurable compute-in-memory (CIM) static random access memory (SRAM) K Roy, A Agrawal, MFA Ali, I Chakraborty, A Ankit, U Saxena US Patent 11,929,141, 2024 | | 2024 |
| McQueen: Mixed Precision Quantization of Early Exit Networks U Saxena, K Roy | | 2023 |
| Partial-Sum Quantization for Near ADC-Less Compute-In-Memory Accelerators U Saxena, K Roy 2023 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2023 | | 2023 |
Kaushik RoyProfessor of Electrical and Computer Engineering, Purdue UniversityVerified email at purdue.edu
