| Kapre: On-gpu audio preprocessing layers for a quick implementation of deep neural network models with keras K Choi, D Joo, J Kim arXiv preprint arXiv:1706.05781, 2017 | 69 | 2017 |
| An optimal algorithm of adjustable delay buffer insertion for solving clock skew variation problem J Kim, D Joo, T Kim Proceedings of the 50th annual design automation conference, 1-6, 2013 | 36 | 2013 |
| Identification of cichlid fishes from Lake Malawi using computer vision D Joo, Y Kwan, J Song, C Pinho, J Hey, YJ Won PloS one 8 (10), e77686, 2013 | 22 | 2013 |
| Buffer sizing and polarity assignment in clock tree synthesis for power/ground noise minimization H Jang, D Joo, T Kim IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2010 | 20 | 2010 |
| An optimal allocation algorithm of adjustable delay buffers and practical extensions for clock skew optimization in multiple power mode designs KH Lim, D Joo, T Kim IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2013 | 15 | 2013 |
| A fine-grained clock buffer polarity assignment for high-speed and low-power digital systems D Joo, T Kim IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014 | 13 | 2014 |
| Optimal utilization of adjustable delay clock buffers for timing correction in designs with multiple power modes J Kim, D Joo, T Kim Integration 52, 91-101, 2016 | 4 | 2016 |
| Managing clock skews in clock trees with local clock skew requirements using adjustable delay buffers D Joo, T Kim 2015 International SoC Design Conference (ISOCC), 137-138, 2015 | 4 | 2015 |
| Clock buffer polarity assignment utilizing useful clock skews for power noise reduction D Joo, T Kim 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), 226-231, 2016 | 3 | 2016 |
| WaveMin: a fine-grained clock buffer polarity assignment combined with buffer sizing D Joo, T Kim 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC), 522-527, 2011 | 3 | 2011 |
| Clock buffer polarity assignment under useful skew constraints D Joo, T Kim Integration 57, 52-61, 2017 | 2 | 2017 |
| Clock design techniques considering circuit reliability Y Kim, M Kang, KH Lim, S Park, D Joo, T Kim 2011 International SoC Design Conference, 142-145, 2011 | 1 | 2011 |
| Student Member, IEEE, and Taewhan Kim, Senior Member, IEEE (2013),” An Optimal Allocation Algorithm of Adjustable Delay Buffers and Practical Extensions for Clock Skew … KH Lim, D Joo IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 0 | 1 | |
| Bioimage Analyses Using Artificial Intelligence and Future Ecological Research and Education Prospects: A Case Study of the Cichlid Fishes from Lake Malawi Using Deep Learning D Joo, J You, YJ Won Proceedings of National Institute of Ecology 3 (2), 67-72, 2022 | | 2022 |
| Clock Polarity Assignment Methodologies for Designing High-Performance and Robust Clock Trees D Joo 서울대학교 대학원, 2016 | | 2016 |
| Design Methodologies for Reliable Clock Networks D Joo, M Kang, T Kim Journal of Computing Science and Engineering 6 (4), 257-266, 2012 | | 2012 |
