| Half-Select Free and Bit-Line Sharing 9T SRAM for Reliable Supply Voltage Scaling K Shin, W Choi, J Park IEEE Transactions on Circuits and Systems I 99 (99), 1 - 13, 2017 | 54 | 2017 |
| Bit parallel 6T SRAM in-memory computing with reconfigurable bit-precision K Lee, J Jeong, S Cheon, W Choi, J Park 2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020 | 52 | 2020 |
| A Refresh-Less eDRAM Macro With Embedded Voltage Reference and Selective Read for an Area and Power Efficient Viterbi Decoder W Choi, G Kang, J Park IEEE Journal of Solid States Circuits 50 (10), 2451-2462, 2015 | 32 | 2015 |
| A DRAM based physical unclonable function capable of generating >1032 Challenge Response Pairs per 1Kbit array for secure chip authentication Q Tang, C Zhou, W Choi, G Kang, J Park, KK Parhi, CH Kim 2017 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2017 | 30 | 2017 |
| Content addressable memory based binarized neural network accelerator using time-domain signal processing W Choi, K Jeong, K Choi, K Lee, J Park Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018 | 26 | 2018 |
| Low cost ternary content addressable memory using adaptive matchline discharging scheme W Choi, K Lee, J Park 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2018 | 26 | 2018 |
| A Charge-Recycling Assist Technique for Reliable and Low Power SRAM Design W Choi, J Park IEEE Transactions on Circuits and Systems I 63 (8), 1164-1175, 2016 | 19 | 2016 |
| Low cost convolutional neural network accelerator based on bi-directional filtering and bit-width reduction W Choi, K Choi, J Park IEEE Access 6, 14734-14746, 2018 | 17 | 2018 |
| Embedded DRAM-based memory customization for low-cost FFT processor design G Kang, W Choi, J Park IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (12 …, 2017 | 15 | 2017 |
| Half-and-half compare content addressable memory with charge-sharing based selective match-line precharge scheme W Choi, J Park, H Kim, C Park, T Song 2018 IEEE Symposium on VLSI Circuits, 17-18, 2018 | 13 | 2018 |
| A charge-sharing based 8t sram in-memory computing for edge dnn acceleration K Lee, S Cheon, J Jo, W Choi, J Park 2021 58th ACM/IEEE Design Automation Conference (DAC), 739-744, 2021 | 12 | 2021 |
| An energy-quality scalable STDP based sparse coding processor with on-chip learning capability H Kim, H Tang, W Choi, J Park IEEE Transactions on Biomedical Circuits and Systems 14 (1), 125-137, 2020 | 11 | 2020 |
| Adaptive Clock Generation Technique for Variation-Aware Subthreshold Logics W Rim, W Choi, J Park IEEE Transactions on Circuits and Systems II 59 (9), 587-591, 2012 | 10 | 2012 |
| Bit-width Reduction and Customized Register for Low Cost Convolutional Neural Network Accelerator K Choi, W Choi, K Shin, J Park International Symposium on Low Power Electronics (ISLPED), 2017 | 8 | 2017 |
| Domain wall memory-based design of deep neural network convolutional layers J Chung, W Choi, J Park, S Ghosh IEEE Access 8, 19783-19798, 2020 | 7 | 2020 |
| A novel one-body dual laser profile based vibration compensation in 3D scanning Y Lim, W Choi, Y Park, S Oh, Y Kim, J Park Measurement 130, 455-466, 2018 | 7 | 2018 |
| Metal object detection in a wireless high-power transfer system using phase–magnitude variation S Kim, W Choi, Y Lim Electronics 10 (23), 2952, 2021 | 6 | 2021 |
| A 0.46 mm2 On-Chip Compensated Type-III Buck Converter Using an Inner Feedback Loop With a Seamless CCM/DCM Transition Technique J Park, HM Lee, SU Shin, W Choi, SW Hong IEEE Transactions on Power Electronics 35 (5), 4477-4482, 2019 | 5 | 2019 |
| DCPA: approximate adder design exploiting dual carry prediction W Choi, M Shim, H Seok, Y Kim IEICE Electronics Express 18 (23), 20210431-20210431, 2021 | 4 | 2021 |
| Bi-directional FIFO memory and convolution processing device using the same J Park, W Choi US Patent 10,528,640, 2020 | 4 | 2020 |
