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Anuj Pathania
Anuj Pathania
Assistant Professor, University of Amsterdam
Verified email at uva.nl - Homepage
Title
Cited by
Cited by
Year
Integrated CPU-GPU Power Management for 3D Mobile Games
A Pathania, Q Jiao, A Prakash, T Mitra
Design Automation Conference (DAC), 2014
1582014
High-Throughput CNN Inference on Embedded ARM big.Little Multi-Core Processors
S Wang, G Ananthanarayanan, Y Zeng, N Goel, A Pathania, T Mitra
Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2019
1182019
Price Theory Based Power Management for Heterogeneous Multi-Cores
T Somu Muthukaruppan, A Pathania, T Mitra
Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2014
1142014
Power-Performance Modelling of Mobile Gaming Workloads on Heterogeneous MPSoCs
A Pathania, AE Irimiea, A Prakash, T Mitra
Design Automation Conference (DAC), 2015
892015
Neural Network Inference on Mobile SoCs
S Wang, A Pathania, T Mitra
Design & Test (D&T), 2019
692019
Power Density-Aware Resource Management for Heterogeneous Tiled Multicores
H Khdr, S Pagani, E Sousa, L Vahid, A Pathania, F Hannig, M Shafique, ...
Transactions on Computers (TC), 2016
692016
Energy Efficiency for Clustered Heterogeneous Multicores
S Pagani, A Pathania, M Shafique, JJ Chen, J Henkel
Transactions on Parallel and Distributed Systems (TPDS), 2016
512016
HotSniper: Sniper-Based Toolchain for Many-Core Thermal Simulations in Open Systems
A Pathania, J Henkel
Embedded Systems Letters (ESL), 2018
372018
Power Management for Mobile Games on Asymmetric Multi-Cores
A Pathania, S Pagani, M Shafique, J Henkel
International Symposium on Low Power Electronics and Design (ISLPED), 2015
352015
Chordmap: Automated Mapping of Streaming Applications onto CGRA
Z Li, D Wijerathne, X Chen, A Pathania, T Mitra
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2021
322021
HiMap: Fast and Scalable High-Quality Mapping on CGRA via Hierarchical Abstraction
D Wijerathne, Z Li, A Pathania, T Mitra, L Thiele
Design, Automation, and Test in Europe (DATE), 2021
32*2021
Neural Network-based Performance Prediction for Task Migration on S-NUCA Many-Cores
M Rapp, A Pathania, T Mitra, J Henkel
Transactions on Computers (TC), 2020
312020
Power-and Cache-Aware Task Mapping with Dynamic Power Budgeting for Many-Cores
M Rapp, M Sagi, A Pathania, A Herkersdorf, J Henkel
Transactions on Computers (TC), 2019
312019
CASCADE: High Throughput Data Streaming via Decoupled Access-Execute CGRA
D Wijerathne, Z Li, M Karunarathne, A Pathania, T Mitra
Transactions on Embedded Computing Systems (TECS), 2019
302019
Defragmentation of Tasks in Many-Core Architecture
A Pathania, V Venkataramani, M Shafique, T Mitra, J Henkel
Transactions on Architecture and Code Optimization (TACO), 2017
262017
Prediction-Based Task Migration on S-NUCA Many-Cores
M Rapp, A Pathania, T Mitra, J Henkel
Design Automation and Test in Europe (DATE), 2019
242019
Optimal Greedy Algorithm for Many-Core Scheduling
A Pathania, V Venkataramani, M Shafique, T Mitra, J Henkel
Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2016
212016
Task Scheduling for Many-Cores with S-NUCA Caches
A Pathania, J Henkel
Design, Automation & Test in Europe (DATE), 2018
192018
Distributed Fair Scheduling for Many-Cores
A Pathania, V Venkataramani, M Shafique, T Mitra, J Henkel
Design Automation and Test in Europe (DATE), 2016
172016
Distributed Scheduling for Many-Cores Using Cooperative Game Theory
A Pathania, V Vanchinathan, S Muhammad, M Tulika, H Jörg
Design Automation Conference (DAC), 2016
172016
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