Renji Thomas

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	전체	2019년 이후
서지정보	351	105
h-index	7	6
i10-index	7	4

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Radu TeodorescuThe Ohio State Universitycse.ohio-state.edu의 이메일 확인됨
Timothy Normand MillerProfessor of Computer Science, Binghamton Universitybinghamton.edu의 이메일 확인됨
Naser SedaghatiCruise Automationgetcruise.com의 이메일 확인됨
Xiang PanPh.D. in Computer Science, Ohio State Universitycse.ohio-state.edu의 이메일 확인됨
James DinanNVIDIAnvidia.com의 이메일 확인됨
Louis-Noel PouchetColorado State Universitycolostate.edu의 이메일 확인됨
P SadayappanProfessor, Kahlert School of Computing, University of Utahcs.utah.edu의 이메일 확인됨
Josep TorrellasProfessor of Computer Science, University of Illinois Urbana-Champaignillinois.edu의 이메일 확인됨
Dimitrios SkarlatosComputer Science Department, Carnegie Mellon Universitycs.cmu.edu의 이메일 확인됨
Nam Sung KimW.J. ‘Jerry’ Sanders III – AMD, Inc. Endowed Chair Professor and Fellow of ACM/IEEEillinois.edu의 이메일 확인됨
Robert Pilawa-PodgurskiProfessor, EECS, University of California, Berkeleyberkeley.edu의 이메일 확인됨
Ulya R. KarpuzcuElectrical and Computer Engineering, University of Minnesota, Twin-Citiesumn.edu의 이메일 확인됨
Shibin QinUniversity of Illinois at Urbana-Champaignillinois.edu의 이메일 확인됨
Aditya AgrawalSenior Software Engineer, Googleillinois.edu의 이메일 확인됨

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Renji Thomas

Meta Reality Labs

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Computer Architecture


제목 서지정보순 정렬 연도순 정렬 제목순 정렬	인용 인용	연도
Booster: Reactive core acceleration for mitigating the effects of process variation and application imbalance in low-voltage chips TN Miller, X Pan, R Thomas, N Sedaghati, R Teodorescu IEEE International Symposium on High-Performance Comp Architecture, 1-12, 2012	103	2012
VRSync: Characterizing and eliminating synchronization-induced voltage emergencies in many-core processors TN Miller, R Thomas, X Pan, R Teodorescu ACM SIGARCH Computer Architecture News 40 (3), 249-260, 2012	77	2012
Parichute: Generalized turbocode-based error correction for near-threshold caches TN Miller, R Thomas, J Dinan, B Adcock, R Teodorescu 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 351-362, 2010	55	2010
Core Tunneling: Variation-Aware Voltage Noise Mitigation in GPUs R Thomas, K Barber, N Sedaghati, L Zhou, R Teodorescu	32	2016
Mitigating the effects of process variation in ultra-low voltage chip multiprocessors using dual supply voltages and half-speed units TN Miller, R Thomas, R Teodorescu IEEE Computer Architecture Letters 11 (2), 45-48, 2011	32	2011
EmerGPU: Understanding and Mitigating Resonance-Induced Voltage Noise in GPU Architectures R Thomas, N Sedaghati, R Teodorescu IEEE International Symposium on Performance Analysis of Systems and Software, 2016	27	2016
StVEC: A vector instruction extension for high performance stencil computation N Sedaghati, R Thomas, LN Pouchet, R Teodorescu, P Sadayappan 2011 International Conference on Parallel Architectures and Compilation …, 2011	19	2011
Snatch: Opportunistically reassigning power allocation between processor and memory in 3D stacks D Skarlatos, R Thomas, A Agrawal, S Qin, R Pilawa-Podgurski, ... 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture …, 2016	6	2016
Architectural Solutions For Mitigating Voltage Noise in GPUs RGG Thomas The Ohio State University, 2015		2015
A Full Digital Phase Locked Loop R Thomas The Ohio State University, 2010		2010
2012 Index IEEE Computer Architecture Letters Vol. 11 EK Ardestani, J Chang, H Chen, J Chen, S Chen, X Chen, JM Codina, ... Energy 21, 24, 0

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