Low-delay parallel architecture for fractal image compression M Panigrahy, I Chakrabarti, AS Dhar Circuits, Systems, and Signal Processing 35, 897-917, 2016 | 19 | 2016 |
VLSI design of fast fractal image encoder M Panigrahy, I Chakrabarti, AS Dhar 18th International Symposium on VLSI Design and Test, 1-2, 2014 | 6 | 2014 |
Hardware Implementation of CORDIC Algorithm MP A.Sahoo 2018 International Conference on Applied Electromagnetics, Signal Processing …, 2018 | 5 | 2018 |
Review of segmentation and classification techniques in computer-aided detection of brain tumor from MRI S Jena, M Panigrahy, JK Das Proceedings of International Conference on Computational Intelligence and …, 2022 | 2 | 2022 |
FPGA Based Digital Filters Design to Remove Noise from ECG Signal A Bakshi, M Panigrahy, JK Das 2021 IEEE International Symposium on Smart Electronic Systems (iSES), 236-239, 2021 | 2 | 2021 |
Hardware implementation of quadtree based fractal image decoder M Panigrahy, I Chakrabarti, AS Dhar 2016 Twenty Second National Conference on Communication (NCC), 1-6, 2016 | 2 | 2016 |
Brain tumor area detection using Anisotropic Diffusion and Morphological Operations S Jena, M Panigrahy, JK Das 2021 IEEE 2nd International Conference on Applied Electromagnetics, Signal …, 2021 | 1 | 2021 |
Digital Design with Programmable Logic Devices M Panigrahy, S Jena, RL Pradhan Advanced VLSI Design and Testability Issues, 1-15, 2020 | | 2020 |
Memory Efficient Fractal-SPIHT Based Hybrid Image Encoder M Panigrahy, NC Behera, B Vandana, I Chakrabarti, AS Dhar International Symposium on VLSI Design and Test, 376-387, 2017 | | 2017 |
VLSI Architectures for Fractal Image Compression M Panigrahy IIT, Kharagpur, 2016 | | 2016 |
Year of Publication: 2016 M Panigrahy, I Chakrabarti, AS Dhar Signal Processing: Image Communication 19, 393-404, 2004 | | 2004 |
Hardware Architecture for Fractal Image Encoder with Quadtree Partitioning M Panigrahy, I Chakrabarti, AS Dhar International Journal of Computer Applications 975, 8887, 0 | | |