| High-speed VLSI architecture for parallel Reed-Solomon decoder H Lee IEEE transactions on very large scale integration (VLSI) systems 11 (2), 288-294, 2003 | 225 | 2003 |
| A high-speed four-parallel radix-24 FFT/IFFT processor for UWB applications M Shin, H Lee 2008 IEEE International Symposium on Circuits and Systems (ISCAS), 960-963, 2008 | 123 | 2008 |
| Reed-solomon decoder systems for high speed communication and data storage applications H Lee US Patent App. 11/222,435, 2006 | 115 | 2006 |
| A power-aware scalable pipelined Booth multiplier H Lee IEEE International SOC Conference, 2004. Proceedings., 123-126, 2004 | 102 | 2004 |
| A high-speed low-complexity Reed-Solomon decoder for optical communications H Lee IEEE Transactions on Circuits and Systems II: Express Briefs 52 (8), 461-465, 2005 | 97 | 2005 |
| A High-Speed Low-Complexity Modified FFT Processor for High Rate WPAN Applications T Cho, H Lee IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21 (1), 187-191, 2012 | 92 | 2012 |
| A high-speed pipelined degree-computationless modified Euclidean algorithm architecture for Reed-Solomon decoders S Lee, H Lee IEICE Transactions on Fundamentals of Electronics, Communications and …, 2008 | 87 | 2008 |
| Efficient QC-LDPC encoder for 5G new radio TTB Nguyen, T Nguyen Tan, H Lee Electronics 8 (6), 668, 2019 | 86 | 2019 |
| A High-Speed Two-Parallel Radix-24 FFT/IFFT Processor for MB-OFDM UWB Systems J Lee, H Lee IEICE Transactions on Fundamentals of Electronics, Communications and …, 2008 | 77 | 2008 |
| VLSI design of Reed-Solomon decoder architectures H Lee, ML Yu, L Song 2000 IEEE International Symposium on Circuits and Systems (ISCAS) 5, 705-708, 2000 | 76 | 2000 |
| A reduced-complexity architecture for LDPC layered decoding schemes S Kim, GE Sobelman, H Lee IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19 (6 …, 2010 | 71 | 2010 |
| A high performance four-parallel 128/64-point radix-24 FFT/IFFT processor for MIMO-OFDM systems H Liu, H Lee APCCAS 2008-2008 IEEE Asia Pacific Conference on Circuits and Systems, 834-837, 2008 | 66 | 2008 |
| An area-efficient Euclidean algorithm block for Reed-Solomon decoder H Lee IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings., 209-210, 2003 | 55 | 2003 |
| A new low-voltage full adder circuit H Lee, GE Sobelman Proceedings Great Lakes Symposium on VLSI, 88-92, 1997 | 54 | 1997 |
| New low-voltage circuits for XOR and XNOR H Lee, GE Sobelman Proceedings IEEE SOUTHEASTCON'97.'Engineering the New Century', 225-229, 1997 | 53 | 1997 |
| A high-speed low-complexity modified radix-25 FFT processor for gigabit WPAN applications T Cho, H Lee, J Park, C Park 2011 IEEE international symposium of circuits and systems (ISCAS), 1259-1262, 2011 | 52 | 2011 |
| New XOR/XNOR and full adder circuits for low voltage, low power applications H Lee, GE Sobelman Microelectronics Journal 29 (8), 509-517, 1998 | 48 | 1998 |
| Modified Euclidean algorithm block for high-speed Reed-Solomon decoder H Lee Electronics Letters 37 (14), 1, 2001 | 47 | 2001 |
| FPGA-based FIR filters using digit-serial arithmetic H Lee, GE Sobelman Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit …, 1997 | 47 | 1997 |
| A high-speed, low-complexity radix-2 FFT processor for MB-OFDM UWB systems J Lee, H Lee, SI Cho, SS Choi ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, 4719-4722, 2006 | 45 | 2006 |
Gerald SobelmanVerified email at umn.edu
