| Architecture, chip, and package codesign flow for interposer-based 2.5-D chiplet integration enabling heterogeneous IP reuse J Kim, G Murali, H Park, E Qin, H Kwon, VCK Chekuri, NM Rahman, ... IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28 (11 …, 2020 | 79 | 2020 |
| Architecture, Chip, and Package Co-design Flow for 2.5 D IC Design Enabling Heterogeneous IP Reuse. J Kim, G Murali, H Park, E Qin, H Kwon, VCK Chekuri, N Dasari, A Singh, ... Proceedings of the 56th Annual Design Automation Conference 2019, 178:1-178:6, 2019 | 58 | 2019 |
| A spectral convolutional net for co-optimization of integrated voltage regulators and embedded inductors HM Torun, H Yu, N Dasari, VCK Chekuri, A Singh, J Kim, SK Lim, ... 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2019 | 28 | 2019 |
| Chiplet/interposer co-design for power delivery network optimization in heterogeneous 2.5-D ICs J Kim, VCK Chekuri, NM Rahman, MA Dolatsara, HM Torun, ... IEEE Transactions on Components, Packaging and Manufacturing Technology 11 …, 2021 | 23 | 2021 |
| Silicon vs. Organic interposer: PPA and reliability tradeoffs in heterogeneous 2.5 D chiplet integration J Kim, VCK Chekuri, NM Rahman, MA Dolatsara, H Torun, ... 2020 IEEE 38th International Conference on Computer Design (ICCD), 80-87, 2020 | 19 | 2020 |
| Design flow for active interposer-based 2.5-D ICs and study of RISC-V architecture with secure NoC H Park, J Kim, VCK Chekuri, MA Dolatsara, M Nabeel, A Bojesomo, ... IEEE Transactions on Components, Packaging and Manufacturing Technology 10 …, 2020 | 17 | 2020 |
| Worst-case eye analysis of high-speed channels based on Bayesian optimization MA Dolatsara, JA Hejase, WD Becker, J Kim, SK Lim, M Swaminathan IEEE Transactions on Electromagnetic Compatibility 63 (1), 246-258, 2020 | 17 | 2020 |
| RTL-to-GDS tool flow and design-for-test solutions for monolithic 3D ICs H Park, K Chang, BW Ku, J Kim, E Lee, D Kim, A Chaudhuri, S Banerjee, ... Proceedings of the 56th Annual Design Automation Conference 2019, 1-4, 2019 | 11 | 2019 |
| Modeling and benchmarking back end of the line technologies on circuit designs at advanced nodes V Huang, J Kim, S Pentapati, SK Lim, A Naeemi 2020 IEEE International Interconnect Technology Conference (IITC), 37-39, 2020 | 10 | 2020 |
| RTL-to-GDS design tools for monolithic 3D ICs J Kim, G Murali, P Vanna-Iampikul, E Lee, D Kim, A Chaudhuri, ... Proceedings of the 39th International Conference on Computer-Aided Design, 1-8, 2020 | 9 | 2020 |
| Advances in design and test of monolithic 3-D ICs A Chaudhuri, S Banerjee, H Park, J Kim, G Murali, E Lee, D Kim, SK Lim, ... IEEE Design & Test 37 (4), 92-100, 2020 | 9 | 2020 |
| Automated generation of all-digital I/0 library cells for system-in-package integration of multiple dies M Lee, A Singh, HM Torun, J Kim, S Lim, M Swaminathan, ... 2018 IEEE 27th Conference on Electrical Performance of Electronic Packaging …, 2018 | 6 | 2018 |
| Power, performance, area and cost analysis of memory-on-logic face-to-face bonded 3D processor designs A Agnesina, M Brunion, J Kim, A Garcia-Ortiz, D Milojevic, F Catthoor, ... 2021 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2021 | 5 | 2021 |
| Automated I/O library generation for interposer-based system-in-package integration of multiple heterogeneous dies M Lee, A Singh, HM Torun, J Kim, SK Lim, M Swaminathan, ... IEEE Transactions on Components, Packaging and Manufacturing Technology 10 …, 2019 | 3 | 2019 |
| ParaMitE: Mitigating Parasitic CNFETs in the Presence of Unetched CNTs S Banerjee, A Chaudhuri, J Kim, G Murali, M Nelson, SK Lim, ... 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 1-9, 2021 | 1 | 2021 |
| On the design of energy-efficient I/O circuits for interposer-based 2.5 D system-in-package M Lee, J Kim, A Singh, HM Torun, M Swaminathan, S Lim, ... 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference …, 2018 | 1 | 2018 |
| An Effective Block Pin Assignment Approach for Block-Level Monolithic 3-D ICs J Kim, BW Ku, J Yoon, SK Lim IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 7 …, 2021 | | 2021 |
| RTL-to-GDS Design Tools for Monolithic 3D ICs Built with Carbon Nanotube Transistors and Resistive Memory SKL Jinwoo Kim, Heechun Park, Edward Lee, Daehyun Kim, Arjun Chaudhuriy ... Government Microcircuit Applications and Critical Technonogy (GOMACTech), 2020 | | 2020 |
| Enabling Heterogeneous IP Reuse with Interposer-based 2.5D ICs and Custom Interface Protocol SKL Jinwoo Kim, Eric Qin, Heechun Park, Tushar Krishna Government Microcircuit Application and Critical Technology Conference …, 2019 | | 2019 |
Sung Kyu LimProfessor, Georgia Institute of TechnologyVerified email at ece.gatech.edu
