| GANA: Graph convolutional network based automated netlist annotation for analog circuits K Kunal, T Dhar, M Madhusudan, J Poojary, A Sharma, W Xu, SM Burns, ... 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 55-60, 2020 | 68 | 2020 |
| ALIGN: A system for automating analog layout T Dhar, K Kunal, Y Li, M Madhusudan, J Poojary, AK Sharma, W Xu, ... IEEE Design & Test 38 (2), 8-18, 2020 | 46 | 2020 |
| A general approach for identifying hierarchical symmetry constraints for analog circuit layout K Kunal, J Poojary, T Dhar, M Madhusudan, R Harjani, SS Sapatnekar Proceedings of the 39th International Conference on Computer-Aided Design, 1-8, 2020 | 44 | 2020 |
| Area and energy‐efficient physically unclonable function based on k‐winners‐take‐all T Dhar, AR Trivedi Electronics Letters 52 (24), 1978-1980, 2016 | 8 | 2016 |
| Fast and efficient constraint evaluation of analog layout using machine learning models T Dhar, J Poojary, Y Li, K Kunal, M Madhusudan, AK Sharma, SD Manasi, ... Proceedings of the 26th Asia and South Pacific design automation conference …, 2021 | 7 | 2021 |
| The ALIGN open-source analog layout generator: V1. 0 and beyond T Dhar, K Kunal, Y Li, Y Lin, M Madhusudan, J Poojary, AK Sharma, ... Proceedings of the 39th International Conference on Computer-Aided Design, 1-2, 2020 | 6 | 2020 |
| Gana: Graph convolutional network based automated netlist annotation for analog circuits. In 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE) K Kunal, T Dhar, M Madhusudan, J Poojary, A Sharma, W Xu, SM Burns, ... IEEE, 55ś60. https://doi. org/10.23919/DATE48585, 2020 | 5 | 2020 |
| A solitary protection measure against scan chain, fault injection, and power analysis attacks on AES T Dhar, S Bhunia, AR Trivedi 2017 IEEE 60th International Midwest Symposium on Circuits and Systems …, 2017 | 5 | 2017 |
| GNN-based hierarchical annotation for analog circuits K Kunal, T Dhar, M Madhusudan, J Poojary, AK Sharma, W Xu, SM Burns, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023 | 3 | 2023 |
| A charge flow formulation for guiding analog/mixed-signal placement T Dhar, S Ramprasath, J Poojary, S Yaldiz, S Burns, R Harjani, ... 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 148-153, 2022 | 3 | 2022 |
| Machine Learning for Analog Layout SM Burns, H Chen, T Dhar, R Harjani, J Hu, N Karmokar, K Kunal, Y Li, ... Machine Learning Applications in Electronic Design Automation, 505-544, 2022 | 2 | 2022 |
| Aging of current DACs and its impact in equalizer circuits T Dhar, J Poojary, R Harjani, SS Sapatnekar 2021 IEEE International Reliability Physics Symposium (IRPS), 1-6, 2021 | 2 | 2021 |
| An aging model for current DACs, and its application to analyzing lifetime degradation in a wireline equalizer T Dhar, J Poojary, R Harjani, SS Sapatnekar Microelectronics Reliability 142, 114912, 2023 | | 2023 |
| Machine Learning Techniques in Analog Layout Automation T Dhar, K Kunal, Y Li, Y Lin, M Madhusudan, J Poojary, AK Sharma, ... Proceedings of the 2021 International Symposium on Physical Design, 71-72, 2021 | | 2021 |
| Learning from Experience: Applying ML to Analog Circuit Design K Kunal, T Dhar, Y Li, M Madhusudan, J Poojary, AK Sharma, W Xu, ... Proceedings of the 2020 International Symposium on Physical Design, 55-55, 2020 | | 2020 |
| Reliability analysis of a Delay-Locked Loop under HCI and BTI Degradation T Dhar, SS Sapatnekar 2019 IEEE International Reliability Physics Symposium (IRPS), 1-6, 2019 | | 2019 |
Sachin SapatnekarUniversity of Minnesotaumn.edu의 이메일 확인됨
Sachin SapatnekarUniversity of Minnesotaumn.edu의 이메일 확인됨