Vinay B. Y. Kumar
Vinay B. Y. Kumar
Indian Institute of Technology Bombay, Nanyang Technological University
Verified email at ee.iitb.ac.in
Title
Cited by
Cited by
Year
FPGA based high performance double-precision matrix multiplication
VBY Kumar, S Joshi, SB Patkar, H Narayanan
International journal of parallel programming 38 (3), 322-338, 2010
732010
FPGA Based High Performance Double-Precision Matrix Multiplication
VBY Kumar, S Joshi, SB Patkar, H Narayanan
VLSI Design, 2009 22nd International Conference on, 341 - 346, 2009
732009
Method and system for speech recognition
NC Badavne, TM Parng, P Yeh, VKB Yadaiah
US Patent App. 13/705,168, 2013
452013
Framework for application mapping over packet-switched network of fpgas: Case studies
VBY Kumar, P Engineer, M Datar, Y Turakhia, S Agarwal, S Diwale, ...
arXiv preprint arXiv:1508.06823, 2015
52015
Post-quantum secure boot
VBY Kumar, N Gupta, A Chattopadhyay, M Kasper, C Krau▀, ...
2020 Design, Automation & Test in Europe Conference & Exhibition (DATEá…, 2020
42020
Itus: A secure risc-v system-on-chip
VBY Kumar, A Chattopadhyay, J Haj-Yahya, A Mendelson
2019 32nd IEEE International System-on-Chip Conference (SOCC), 418-423, 2019
42019
Relaxation based circuit simulation acceleration over CPU-FPGA
VBY Kumar, K Dhiman, M Datar, A Pacharne, H Narayanan, SB Patkar
2016 29th International Conference on VLSI Design and 2016 15thá…, 2016
32016
A novel duplication based countermeasure to statistical ineffective fault analysis
A Baksi, VBY Kumar, B Karmakar, S Bhasin, D Saha, A Chattopadhyay
Australasian Conference on Information Security and Privacy, 525-542, 2020
22020
FPGA-based Implementation of M4RM for Matrix Multiplication over GF (2)
V Kumar, VBY Kumar, SB Patkar
18th International Symposium on VLSI Design and Test, 1-2, 2014
12014
Projective Geometry and precedence constraint based application mapping on multicore network-on-chip systems
J Porwal, S Diwale, VBY Kumar, SB Patkar
Technical Papers of 2014 International Symposium on VLSI Design, Automationá…, 2014
12014
Towards Designing a Secure RISC-V System-on-Chip: ITUS
VBY Kumar, S Deb, N Gupta, S Bhasin, J Haj-Yahya, A Chattopadhyay, ...
Journal of Hardware and Systems Security 4 (4), 329–342, 2020
2020
Secure Your SoC: Building System-on-Chip Designs for Security
S Bhasin, TE Carlson, A Chattopadhyay, VBY Kumar, A Mendelson, ...
2020
Recruiting Fault Tolerance Techniques for Microprocessor Security
VBY Kumar, S Deb, R Kumar, M Khairallah, A Chattopadhyay, ...
2019 IEEE 28th Asian Test Symposium (ATS), 80-805, 2019
2019
Lightweight Forth Programmable NoCs
VBY Kumar, D Shah, M Datar, SB Patkar
2018 31st International Conference on VLSI Design and 2018 17thá…, 2018
2018
Parallel two step random walk algorithm to analyze VLSI power grid networks
S Dash, V Bangera, VBY Kumar, G Trivedi, SB Patkar
2015 19th International Symposium on VLSI Design and Test, 1-2, 2015
2015
Storage-allocation to sequential structures in High-Level Synthesis-assisted prototyping
VBY Kumar, S Maity, SB Patkar
2014 IEEE 32nd International Conference on Computer Design (ICCD), 464-469, 2014
2014
Hardware-software Scalable Architectures for Gaussian Elimination over GF (2) and Higher Galois Fields.
P Saxena, VBY Kumar, D Singh, H Narayanan, SB Patkar
PECCS, 195-201, 2013
2013
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Articles 1–17