Æȷοì
Sayandeep Sanyal
Sayandeep Sanyal
Senior Formal Verification Engineer, Qualcomm
ieee.orgÀÇ À̸ÞÀÏ È®ÀεÊ
Á¦¸ñ
Àοë
Àοë
¿¬µµ
Fault Classification and Coverage of Analog Circuits using DC Operating Point and Frequency Response Analysis
S Sanyal, SPPK Garapati, A Patra, P Dasgupta, M Bhattacharya
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 123-128, 2019
92019
A Structured Approach for Rapid Identification of Fault-Sensitive Nets in Analog Circuits
S Sanyal, A Patra, P Dasgupta, M Bhattacharya
2019 IEEE 28th Asian Test Symposium (ATS), 135-1355, 2019
82019
CoveRT: A Coverage Reporting Tool for Analog Mixed-Signal Designs
S Sanyal, A Hazra, P Dasgupta, S Morrison, S Surendran, ...
2020 33rd International Conference on VLSI Design and 2020 19th ¡¦, 2020
52020
Recurrence in Dense-time AMS Assertions
S Sanyal, AAB da Costa, P Dasgupta
IEEE Transactions on Computer-Aided Design of Integrated Circuits and ¡¦, 2020
42020
The Notion of Cross Coverage in AMS Design Verification
S Sanyal, A Hazra, P Dasgupta, S Morrison, S Surendran, ...
2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), 217-222, 2020
32020
A Framework for Automated Feature Based Mixed-Signal Equivalence Checking
A Ain, S Sanyal, P Dasgupta
VLSI Design and Test: 21st International Symposium, VDAT 2017, Roorkee ¡¦, 2017
32017
The CoveRT Approach for Coverage Management in Analog and Mixed-Signal Integrated Circuits
S Sanyal, P Dasgupta, A Hazra, S Das, S Morrison, S Surendran, ...
IEEE Transactions on Computer-Aided Design of Integrated Circuits and ¡¦, 2022
12022
A Methodology for Identification of Internal Nets for Improving Fault Coverage in Analog and Mixed Signal Circuits
S Sanyal, M Bhattacharya, A Patra, P Dasgupta
Journal of Electronic Testing 36, 719-730, 2020
12020
Fault Vulnerability Ranking of Transistors in Analog Integrated Circuits using AC Analysis
SPPK Garapati, S Sanyal, A Patra, P Dasgupta, M Bhattacharya
2020 IEEE International Test Conference India, 1-8, 2020
12020
Identifying glitches and levels in mixed-signal waveforms
S Sanyal, P Dasgupta, A Hazra, S Morrison, S Surendran, ...
US Patent App. 18/071,917, 2023
2023
Analog Coverage-driven Selection of Simulation Corners for AMS Integrated Circuits
S Sanyal, A Hazra, P Dasgupta, S Morrison, S Surendran, ...
2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2023
2023
Transistor—level defect coverage and defect simulation
M Bhattacharya, S Sanyal, A Patra, P Dasgupta
US Patent 11,620,424, 2023
2023
Accelerating Defect Simulation in Analog and Mixed-Signal Circuits by Parallel Defect Injection
S Sanyal, M Bhattacharya, P Dasgupta, A Patra
2023 36th International Conference on VLSI Design and 2023 22nd ¡¦, 2023
2023
CoVerPlan: A Comprehensive Verification Planning Framework Leveraging PSS Specifications
S Das, S Sanyal, A Hazra, P Dasgupta
ACM Transactions on Design Automation of Electronic Systems 28 (1), 1-32, 2022
2022
Tracking Coverage Artefacts for Periodic Signals using Sequence-based Abstractions
A Chakraborty, S Sanyal, P Dasgupta, A Hazra, S Morrison, S Surendran, ...
2022 35th International Conference on VLSI Design and 2022 21st ¡¦, 2022
2022
A machine learning approach for choosing component level conditions for prognostics of AMS systems
S Sanyal, A Ain, P Dasgupta
2018 International Symposium on Devices, Circuits and Systems (ISDCS), 1-6, 2018
2018
ÇöÀç ½Ã½ºÅÛÀÌ ÀÛµ¿µÇÁö ¾Ê½À´Ï´Ù. ³ªÁß¿¡ ´Ù½Ã ½ÃµµÇØ ÁÖ¼¼¿ä.
ÇмúÀÚ·á 1–16