| Rationale for a 3D heterogeneous multi-core processor E Rotenberg, BH Dwiel, E Forbes, Z Zhang, R Widialaksono, ... 2013 IEEE 31st International Conference on Computer Design (ICCD), 154-168, 2013 | 37 | 2013 |
| AnyCore: A synthesizable RTL model for exploring and fabricating adaptive superscalar cores RBR Chowdhury, AK Kannepalli, S Ku, E Rotenberg 2016 IEEE International Symposium on Performance Analysis of Systems and …, 2016 | 16 | 2016 |
| Under 100-cycle thread migration latency in a single-isa heterogeneous multi-core processor E Forbes, Z Zhang, R Widialaksono, B Dwiel, RBR Chowdhury, ... 2015 IEEE Hot Chips 27 Symposium (HCS), 1-1, 2015 | 13 | 2015 |
| Post-silicon cpu adaptation made practical using machine learning SJ Tarsa, RBR Chowdhury, J Sebot, G Chinya, J Gaur, ... 2019 ACM/IEEE 46th Annual International Symposium on Computer Architecture …, 2019 | 10 | 2019 |
| Experiences with Two FabScalar-based Chips E Forbes, RBR Chowdhury, B Dwiel, A Kannepalli, V Srinivasan, Z Zhang, ... 6th Workshop on Architectural Research Prototyping (WARP-6), 2015 | 8 | 2015 |
| H3 (Heterogeneity in 3D): A Logic-on-Logic 3D-Stacked Heterogeneous Multi-Core Processor V Srinivasan, RBR Chowdhury, E Forbes, R Widialaksono, Z Zhang, ... 2017 IEEE 35th International Conference on Computer Design (ICCD), 145-152, 2017 | 6 | 2017 |
| Physical Design of a 3D-Stacked Heterogeneous Multi-Core Processor R Widialaksono, R Basu Roy Chowdhury, Z Zhang, J Schabel, S Lipa, ... 3DIC 2016, 2016 | 5 | 2016 |
| AnyCore: Design, Fabrication, and Evaluation of Comprehensively Adaptive Superscalar Processors RBR Chowdhury North Carolina State University, 2016 | 3 | 2016 |
| Design methodology internal sub state observer using CPLD J RoyChoudhury, TP Banerjee, A Nathvani, RBR Chowdhury, ... 2009 World Congress on Nature & Biologically Inspired Computing (NaBIC …, 2009 | 3 | 2009 |
| Slipstream Processors Revisited: Exploiting Branch Sets V Srinivasan, RBR Chowdhury, E Rotenberg 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture …, 2020 | 2 | 2020 |
| Diligent TLBs: a mechanism for exploiting heterogeneity in TLB miss behavior H Elnawawy, RBR Chowdhury, A Awad, GT Byrd Proceedings of the ACM International Conference on Supercomputing, 195-205, 2019 | 2 | 2019 |
| FabScalar RISC-V RBR Chowdhury, AK Kannepalli, E Rotenberg 2nd RISC-V Workshop, 2015 | 2 | 2015 |
| Inter-cluster communication of live-in register values S Pediaditaki, E Schuchman, RBR Chowdhury, M Shevgoor US Patent 10,437,590, 2019 | 1 | 2019 |
| Translation table entry prefetching in dynamic binary translation based processor G Venkatasubramanian, JM Agron, C Pereira, G Hinton, S Winkel, ... US Patent App. 15/839,310, 2019 | 1 | 2019 |
| Management of the untranslated to translated code steering logic in a dynamic binary translation based processor G Venkatasubramanian, JM Agron, C Pereira, RBR Chowdhury US Patent App. 15/823,387, 2019 | 1 | 2019 |
| AnyCore-1: A Comprehensively Adaptive 4-Way Superscalar Processor R Basu Roy Chowdhury, AK Kannepalli, A Rotenberg Hot Chips 28 Symposium (HCS), 2016 IEEE, 1-1, 2016 | 1* | 2016 |
| Hardware profiler to track instruction sequence information including a blacklisting mechanism and a whitelisting mechanism S Bhattacharya, M Dechene, J Faistl, JM Agron, S Winkel, ... US Patent App. 16/233,035, 2020 | | 2020 |
| Reducing microprocessor power with minimal performance impact by dynamically adapting runtime operating configurations using machine learning J Sebot, RBR Chowdhury, R Miftakhutdinov, SJ Tarsa, GN Chinya, ... US Patent App. 16/370,572, 2020 | | 2020 |
| Management of the untranslated to translated code steering logic in a dynamic binary translation based processor G Venkatasubramanian, JM Agron, C Pereira, RBR Chowdhury US Patent App. 16/777,063, 2020 | | 2020 |
| Translation pinning in translation lookaside buffers RBR Chowdhury, H Elnawawy, A Awad US Patent App. 15/843,165, 2019 | | 2019 |
Eric RotenbergNorth Carolina State Universityncsu.edu의 이메일 확인됨
