| GaSb-InAs n-TFET with doped source underlap exhibiting low subthreshold swing at sub-10-nm gate-lengths A Sharma, AA Goud, K Roy Electron Device Letters, IEEE 35 (12), 1221-1223, 2014 | 56 | 2014 |
| Source-Underlapped GaSb-InAs TFETs With Applications to Gain Cell Embedded DRAMs A Sharma, AG Akkala, JP Kulkarni, K Roy IEEE Transactions on Electron Devices, 2016 | 23 | 2016 |
| Asymmetric Underlapped Sub-10nm n-FinFETs for High-Speed and Low-Leakage 6T SRAMs AG Akkala, R Venkatesan, A Raghunathan, K Roy IEEE Transactions on Electron Devices 63 (3), 1034 - 1040, 2015 | 23 | 2015 |
| Atomistic tight-binding based evaluation of impact of gate underlap on source to drain tunneling in 5 nm gate length Si FinFETs AA Goud, SK Gupta, SH Choday, K Roy 71st Device Research Conference, 51-52, 2013 | 21 | 2013 |
| Asymmetric underlapped FinFET based robust SRAM design at 7nm node AA Goud, R Venkatesan, A Raghunathan, K Roy Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015 …, 2015 | 16 | 2015 |
| P-channel Tunneling Field Effect Transistor (TFET): Sub-10nm technology enablement by GaSb-InAs with doped source underlap A Sharma, AA Goud, K Roy Device Research Conference (DRC), 2015 73rd Annual, 151-152, 2015 | 13 | 2015 |
| Design space exploration of FinFETs in sub-10nm technologies for energy-efficient near-threshold circuits SK Gupta, WS Cho, AA Goud, K Yogendra, K Roy 71st Device Research Conference, 117-118, 2013 | 13 | 2013 |
| Sub-10 nm FinFETs and tunnel-FETs: From devices to systems A Sharma, AA Goud, K Roy 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015 | 10 | 2015 |
| NEGF simulation of electron transport in resonant tunneling and resonant interband tunneling diodes AG Akkala Purdue University, 2011 | 8 | 2011 |
| Asymmetric Underlapped FinFETs for Near- and Super-threshold Logic at Sub-10nm Technology Nodes AA Goud, R Venkatesan, A Raghunathan, K Roy ACM Journal on Emerging Technologies in Computing Systems (JETC) 13 (2), 23 …, 2017 | 2 | 2017 |
| InAs-Al hybrid devices passing the topological gap protocol M Quantum Phys. Rev. B 107 (24), 2023 | | 2023 |
| Asymmetric underlap optimization of sub-10nm finfets for realizing energy-efficient logic and robust memories AG Akkala Purdue University, 2016 | | 2016 |
