| Design of novel reversible logic gate with enhanced traits MK Singh, R Nakkeeran 2017 IEEE International Conference on Inventive Computing and Informatics …, 2017 | 11 | 2017 |
| A low power 8 × 2^7-1 PRBS generator using Exclusive-OR gate merged D flip-flops MK Singh, P Singh, DM Das, M Sakare 2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS …, 2021 | 4 | 2021 |
| A PRBS Generator Using Merged XOR-D Flip-Flop as Building Blocks MK Singh, P Singh, U Chichhula, H Mehra, DM Das, M Sakare Circuits, Systems, and Signal Processing 42 (11), 6813-6828, 2023 | 1 | 2023 |
| A Low Power Differential Delay Cell without Cross-Coupled Latch for Ring VCO MK Singh, P Singh, DM Das, M Sakare 2023 18th Conference on Ph. D Research in Microelectronics and Electronics …, 2023 | 1 | 2023 |
| Frequency Range Enhancement in Differential Ring VCO while Maintaining Phase Noise Performance MKS Puneet Singh, Naveen Kadayinti, Devarshi Das, Mahendra Sakare Techrxiv, 2023 | 1* | 2023 |
| Design of a PRBS generator and a serializer using active inductor employed CML latch P Singh, MK Singh, VG Hande, M Sakare 2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS …, 2021 | 1 | 2021 |
| A single-tank quadrature voltage-controlled oscillator (QVCO) and method of operation therof MS Mayank K Singh, Hirensh Mehra, R. Nagulapalli IN Patent App. 202,411,009,384, 2024 | | 2024 |
| An electronic device and fabrication method thereof MS Mayank K Singh, Upendra Chichula, R. Nagulapalli US Patent App. 18/617,417, 2024 | | 2024 |
| A phase frequency detector and its method of operation therof MS Mayank K Singh, Hirensh Mehra, R. Nagulapalli IN Patent App. 202,411,016,895, 2024 | | 2024 |
| A circuit facilitating optimization of data frequency and power consumption and a method thereof MS Mayank K Singh, Puneet Singh US Patent App. 18/393,261, 2023 | | 2023 |
| An electronic device and fabrication method thereof MS Mayank K Singh, Upendra Chichula, R. Nagulapalli IN Patent App. 202,311,081,510, 2023 | | 2023 |
| Bandgap Reference Circuit for Generating BGR Voltage and a method thereof MKS Sakare Mahendra, R. Nagulapalli US Patent App. 18/373,713, 2023 | | 2023 |
| Bandgap Reference Circuit for Generating BGR Voltage and a method thereof MKS Sakare Mahendra, R. Nagulapalli IN Patent App. 202,311,046,972, 2023 | | 2023 |
| An active inductor employed CML latch for high speed integrated circuits P Singh, MK Singh, VG Hande, M Sakare Analog Integrated Circuits and Signal Processing 114 (3), 277-286, 2023 | | 2023 |
| A differential delay cell for ring oscillators P Singh, MK Singh, M Sakare Techrxiv, 2023 | | 2023 |
| Constant Slope Circuit and Method for Optimizing Duty Cycle of an Electronics Device MK Singh, P Singh, M Sakare IN Patent App. 202,211,007,271, 2022 | | 2022 |
| Pseudo-random binary sequences (PRBS) generator for performing on-chip testing and a method thereof M Sakare, MK Singh, P Singh, D Das, Vinayak, Hande US Patent US20220317181A1, 2022 | | 2022 |
| A symmetrical differential exclusive OR (XOR) gate P Singh, MK Singh, M Sakare IN Patent App. 202,111,059,328, 2021 | | 2021 |
| Pseudo-random binary sequences (PRBS) generator for performing on-chip testing and a method thereof MK Singh, M Sakare, P Singh IN Patent App. 202,111,012,409, 2021 | | 2021 |
| Design of Different Reversible Logic Gate with Improved Parametric Attributes using GDI Technique MKS R Nakkeeran IEEE VLSI Circuits and Systems Letter 4 (4), 27-35, 2018 | | 2018 |
Mahendra SakareAssistant Professor, Indian Institute of Techonology RoparVerified email at iitrpr.ac.in
