| Pi-gate soi mosfet JT Park, JP Colinge, CH Diaz IEEE Electron Device Letters 22 (8), 405-406, 2001 | 470 | 2001 |
| Self-aligned wrapped-around structure JP Colinge, KC Ching, TP Guo, CH Diaz US Patent 9,209,247, 2015 | 410 | 2015 |
| An experimentally validated analytical model for gate line-edge roughness (LER) effects on technology scaling CH Diaz, HJ Tao, YC Ku, A Yen, K Young IEEE Electron device letters 22 (6), 287-289, 2001 | 229 | 2001 |
| Dynamic gate coupling of NMOS for efficient output ESD protection C Duvvury, C Diaz Proc. IRPS 30, 141-150, 1992 | 191 | 1992 |
| Stress memorization technique (SMT) by selectively strained-nitride capping for sub-65nm high-performance strained-Si device application CH Chen, TL Lee, TH Hou, CL Chen, CC Chen, JW Hsu, KL Cheng, ... Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004., 56-57, 2004 | 173 | 2004 |
| Multi-gate device and method of fabrication thereof KC Ching, CW Tsai, CH Diaz, CH Wang, WY Lien, YK Leung US Patent 9,818,872, 2017 | 171 | 2017 |
| Method of fabricating a silicon-on-insulator semiconductor device with an implanted ground plane JP Colinge, CH Diaz US Patent 6,391,752, 2002 | 142 | 2002 |
| Exploiting CMOS reverse interconnect scaling in multigigahertz amplifier and oscillator design B Kleveland, CH Diaz, D Vook, L Madden, TH Lee, SS Wong IEEE Journal of Solid-State Circuits 36 (10), 1480-1488, 2001 | 141 | 2001 |
| Quasi-surrounding gate and a method of fabricating a silicon-on-insulator semiconductor device with the same JP Colinge, CH Diaz US Patent 6,359,311, 2002 | 139 | 2002 |
| Monolithic CMOS distributed amplifier and oscillator B Kleveland, CH Diaz, D Vock, L Madden, TH Lee, SS Wong 1999 IEEE International Solid-State Circuits Conference. Digest of Technical …, 1999 | 134 | 1999 |
| Multi-gate device and method of fabrication thereof KC Ching, CF Huang, CH Diaz, CH Wang, WH Hsieh, YK Leung US Patent 9,887,269, 2018 | 131 | 2018 |
| Formation of an indium retrograde profile via antimony ion implantation to improve NMOS short channel effect HCH Wang, SY Lu, MC Chiang, CH Diaz US Patent 6,500,739, 2002 | 129 | 2002 |
| Non-volatile memory device having nanocrystal floating gate and method of fabricating same JP Colinge, CH Diaz US Patent 9,899,398, 2018 | 106 | 2018 |
| A scaleable model for STI mechanical stress effect on layout dependence of MOS electrical characteristics KW Su, YM Sheu, CK Lin, SJ Yang, WJ Liang, X Xi, CS Chiang, JK Her, ... Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003 …, 2003 | 104 | 2003 |
| Circuit-level electrothermal simulation of electrical overstress failures in advanced MOS I/O protection devices CH Diaz, SM Kang, C Duvvury IEEE transactions on computer-aided design of integrated circuits and …, 1994 | 101 | 1994 |
| Achieving uniform nMOS device power distribution for sub-micron ESD reliability Duvvury, Diaz, Haddock 1992 International Technical Digest on Electron Devices Meeting, 131-134, 1992 | 101 | 1992 |
| Cmos technology for ms/rf soc CH Diaz, DD Tang, JYC Sun IEEE Transactions on Electron Devices 50 (3), 557-566, 2003 | 100 | 2003 |
| Leakage scaling in deep submicron CMOS for SoC YS Lin, CC Wu, CS Chang, RP Yang, WM Chen, JJ Liaw, CH Diaz IEEE Transactions on electron devices 49 (6), 1034-1041, 2002 | 96 | 2002 |
| Modeling mechanical stress effect on dopant diffusion in scaled MOSFETs YM Sheu, SJ Yang, CC Wang, CS Chang, LP Huang, TY Huang, ... IEEE transactions on electron devices 52 (1), 30-38, 2004 | 91 | 2004 |
| Horizontal gate-all-around device having wrapped-around source and drain CH Lin, CC Wu, CH Diaz, CH Wang, WH Hsieh, YM Sheu US Patent 10,109,721, 2018 | 89 | 2018 |
