Jared Zerbe

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	All	Since 2019
Citations	10761	3801
h-index	55	32
i10-index	164	90

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Co-authors

Mark HorowitzProfessor of Electrical Engineering and Computer ScienceVerified email at ee.stanford.edu
Carl WernerRambusVerified email at ieee.org
Stefanos Sidiropoulos.Verified email at alumni.stanford.edu
Don StarkEngineering Director, GoogleVerified email at google.com
Vladimir StojanovicProfessor of Electrical Engineering and Computer Sciences, University of CaliforniaVerified email at berkeley.edu
Masum HossainU of AVerified email at ualberta.ca
Ramin FarjadVerified email at alumni.stanford.edu
Elad AlonProfessor of Electrical Engineering and Computer SciencesVerified email at berkeley.edu
AssaderaghiSiTimeVerified email at sitime.com
Amir AmirkhanyHead of Samsung Display America LabVerified email at stanfordalumni.org
Jaeha KimElectrical and Computer Engineering, Seoul National University, KoreaVerified email at snu.ac.kr
John M WilsonNVIDIA Circuits Research GroupVerified email at nvidia.com
Chih-Kong Ken YangProfessor of Electrical Engineering, UCLAVerified email at ee.ucla.edu
Dustin DunwellPh.D. Candidate, University of TorontoVerified email at utoronto.ca
Anthony Chan CarusoneProfessor of Electrical Engineering, University of TorontoVerified email at isl.utoronto.ca
Chuck YuanAppleVerified email at apple.com
Fred S. LeeDisplay Module Architecture Lead, Apple Inc.Verified email at alum.mit.edu
Sanjay PantApple Inc.Verified email at apple.com
Borivoje NikolicUniversity of California BerkeleyVerified email at berkeley.edu
Socrates VamvakosVerified email at rambus.com

Jared Zerbe

Director of Engineering, Apple

Verified email at alumni.stanford.edu

Analog mixed signal circuit design computer architecture


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Integrating receiver with precharge circuitry JL Zerbe, BW Garlepp, PS Chau, KS Donnelly, MA Horowitz, ... US Patent 8,199,859, 2012	516	2012
A portable digital DLL for high-speed CMOS interface circuits BW Garlepp, KS Donnelly, J Kim, PS Chau, JL Zerbe, C Huang, CV Tran, ... IEEE Journal of solid-state circuits 34 (5), 632-644, 1999	361	1999
Equalization and clock recovery for a 2.5-10-Gb/s 2-PAM/4-PAM backplane transceiver cell JL Zerbe, CW Werner, V Stojanovic, F Chen, J Wei, G Tsang, D Kim, ... IEEE Journal of Solid-State Circuits 38 (12), 2121-2130, 2003	359	2003
Bus system optimization JLV Zerbe, KS Donnelly, S Sidiropoulos, DC Stark, MA Horowitz, L Yu, ... US Patent 6,643,787, 2003	314	2003
A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 megabyte/s DRAM TH Lee, KS Donnelly, JTC Ho, J Zerbe, MG Johnson, T Ishikawa IEEE Journal of Solid-State Circuits 29 (12), 1491-1496, 1994	305	1994
Apparatus and method for topography dependent signaling MA Horowitz, RM Barth, CE Hampel, A Moncayo, KS Donnelly, JL Zerbe US Patent 6,321,282, 2001	288	2001
Optimized power supply for an electronic system JLV Zerbe, J Kim, YU Frans, HM Nguyen US Patent 8,362,642, 2013	261	2013
Method and apparatus for receiving high speed signals with low latency JL Zerbe US Patent 6,396,329, 2002	238	2002
Low-latency equalization in multi-level, multi-line communication systems PS Chau, HJ Liaw, J Kim, JL Zerbe US Patent 7,269,212, 2007	229	2007
Autonomous dual-mode (PAM2/4) serial link transceiver with adaptive equalization and data recovery V Stojanovic, A Ho, BW Garlepp, F Chen, J Wei, G Tsang, E Alon, ... IEEE Journal of Solid-State Circuits 40 (4), 1012-1026, 2005	210	2005
Partial response receiver VM Stojanovic, MA Horowitz, JL Zerbe, A Bessios, ACC Ho, JC Wei, ... US Patent 7,397,848, 2008	174	2008
Error detection and offset cancellation during multi-wire communication JM Kizer, J Wilson, L Luo, F Ware, JL Zerbe US Patent 8,462,891, 2013	159	2013
Apparatus and method for topography dependent signaling MA Horowitz, RM Barth, CE Hampel, A Moncayo, KS Donnelly, JL Zerbe US Patent 6,516,365, 2003	156	2003
High-speed signaling systems with adaptable pre-emphasis and equalization JL Zerbe, FF Chen, A Ho, R Farjad-Rad, JW Poulton, KS Donnelly, ... US Patent 9,137,063, 2015	152	2015
Clock recovery circuit M Hossain, JL Zerbe, MJ Park US Patent 9,036,764, 2015	150	2015
Method and apparatus for evaluating and optimizing a signaling system J Zerbe, PS Chau, WF Stonecypher US Patent 7,490,275, 2009	150	2009
Integrated circuit with timing adjustment mechanism and method JL Zerbe, KS Donnelly, S Sidiropoulos, DC Stark, MA Horowitz, L Yu, ... US Patent 6,950,956, 2005	146	2005
Calibrated data communication system and method JL Zerbe, KS Donnelly, S Sidiropoulos, DC Stark, MA Horowitz, L Yu, ... US Patent 7,042,914, 2006	145	2006
Transparent multi-mode PAM interface JL Zerbe, CW Werner, WF Stonecypher, FF Chen US Patent 7,308,058, 2007	140	2007
Partial response receiver with clock data recovery BW Garlepp, JL Zerbe, M Jeeradit, VM Stojanovic US Patent 7,433,397, 2008	130	2008

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